1. Field of the Invention
The present invention relates to a semiconductor device, a receiver circuit and a frequency multiplier circuit, and particularly to a receiver circuit part corresponding to a receiver of a Low Voltage Differential Signal (LVDS) circuit capable of low voltage differential transmission.
2. Background
In recent years, a low voltage differential signal transmission technology using so-called LVDS circuits has become popular for attempting to satisfy demands of high speed data transmission.
The LVDS is a standard of cables for connecting, for example, graphic controllers of personal computers with liquid crystal displays. Since a low voltage and a differential signal are used, it has features of preventing Electro-Magnetic Interference (EMI) noises from being emitted and of being durable against foreign noises (See for example Japanese Unexamined Patent Publication No. 2002-232490).
The LVDS is mainly used for image data transmission in personal computers, and frequencies of transmission clock (dot clock) signals differ in accordance with image sizes (i.e., panel sizes). The frequencies of the clock signals are typically in a range between 20 MHz and 160 MHz.
The LVDS circuit is provided with data lines for, for example, four channels and a clock line parallel to each other between a driver (also referred to as a transceiver) on the personal computer side and a receiver on the liquid crystal panel side, the clock line transmitting a clock signal CK having a period corresponding to one dot clock (the period of one dot clock corresponds a duration of, for example, seven data bits transmitted through the data lines, namely seven periods thereof) of the liquid crystal panel. The data lines for one channel are composed of a pair of lines each transmitting the data signal having a phase opposite to each other. The pair of transmission lines for transmitting the data signals opposite in phase to each other is referred to as balanced transmission lines.
As described above, the LVDS circuit is configured to transmit one signal with a pair of transmission lines.
The receiver, on a receiving side of the LVDS circuit, is provided with four sampling circuits as data latch circuits, each receiving one of the four channels of serial data respectively transmitted through the four channels of data lines and converting the serial data into parallel data, and a clock generator circuit that receives the clock signal transmitted through one channel of the clock lines and generates sampling clock signals CK1 through CK7 used for data latch for converting by one clock (CK) unit (i.e., seven data clock signals) the serial data respectively input to the four sampling circuits into the parallel data.
As the clock generator circuit, a Delay Locked Loop (DLL) circuit is used. As the sampling circuit, a serial-parallel converter circuit is used that is capable of sampling seven unit data contained in one clock unit forming the serial input data.
The DLL circuit is composed of a phase comparator circuit, a charge pump circuit, a low pass filter (hereinafter referred to as LPF), a DLL bias circuit, a delay circuit including a plurality of unit delay circuits, and a sampling clock generating circuit. In this circuit, the unit delay circuits are connected in series, wherein at least one of the former unit delay circuits are provided as, for example, dummies, the clock signal CK is input to at least one of the unit delay circuits of the former dummies, the input signal of the first unit delay circuit except the dummies is input to one of input terminals of the phase comparator, and the output signal of the last unit delay circuit is fed back to the other of the input terminals of the phase comparator, and clock signals with multiple phases are output from the first through the last unit delay circuits except the dummies.
The amount of delay in each of the unit delay circuits changes in accordance with a control voltage and controlled so that the clock signals CK with multiple phases output form the first unit delay circuit and the last unit delay circuit except the dummies are in phase. As a result, the seven clock signals having phases shifted by a seventh of the period with each other can be generated. Then, the non-overlapping (with no temporal overlapping) sampling clock signals CK1 through CK7 are generated by the sampling clock generator circuit based on the seven clock signals with multiple phases, which can be supplied to the serial-parallel converter circuit, the sampling circuit, as signals for data sampling.
Conventional DLL circuits have a problem that the delays of the output clock signals from the DLL circuits with respect to the input clock signals to the DLL circuits vary in accordance with frequencies of the input clock signals. This causes a further problem that, when sampling the input data by the output clock signals from the DLL circuits, the setup time or the hold time is not sufficient to correctly latch the data.
Accordingly, the present invention addresses the above problem and has an advantage of providing a semiconductor device, a receiver circuit, and a frequency multiplier circuit capable of keeping the delay of the output clock signal from the DLL circuit with respect to the input clock signal to the DLL circuit to stably maintain the setup time and the hold time for the input data.